The use of an underlying buffer is one of the most investigated stress techniques to grow strained silicon planar, fin-shaped or wire-shaped channels.
For silicon channels, generating a compressive strain in the direction from source to drain in the channel is beneficial for p-type Field Effect Transistors (p-FETs). However suitable underlying buffers are hard to find. One option is the use of a carbon-doped Si buffer as described in Arimoto, et al. (Journal of Crystal Growth, 378, 201, 212-217 (2013)), but this option comes with severe integration challenges. For instance, it is difficult to keep the carbon in a substitutional lattice position during processing and therefore to maintain the induced strain.
For germanium channels, generating a tensile strain in the direction from source to drain in the channel is beneficial for n-type FETs. Current investigations focus on the use of a SiGeSn buffer layer (Beller et al., Appl. Phys. Lett. 101, 221111 (2012)). The use of such a buffer layer is however very problematic because it suffers from a small band gap which leads to an inversed hetero-offset in the device, which has a negative impact on device performances.
Another issue with buffers of conventional devices is that it is very difficult to selectively remove the buffer after the group IV channel growth. This makes for instance the formation of Gate All Around (GAA) FETs particularly challenging.
There is therefore still a need in the art for alternative buffers for introducing strain in group IV semiconductor structures and which would not suffer from one or more of the drawbacks of conventional devices.